---------------------------------------------------------------------------------
  -- Design Name : work.UserPkg.IdRegs32_32 Test Bench
  -- File Name   : IdRegs32_32.vht
  -- Function    : work.UserPkg.IdRegs32_32 test bench
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use work.TBPkg.all;
use work.UserPkg.all;

entity IdRegs32_32_vhd_tst is
  -- this page is intentionally left blank
end IdRegs32_32_vhd_tst;

architecture IdRegs32_32_arch of IdRegs32_32_vhd_tst is
  -- constants
  -- signals
  signal clk      : std_logic;
  signal rs1			: RegAddr;
  signal rs2			: RegAddr;
  signal wr				: std_logic;
	signal cl				: std_logic;
  signal rwr			: RegAddr;
	signal rwr16		: std_logic;
  signal rwr_data : word32;
  signal rs1_data : word32;
  signal rs2_data : word32;
begin
  
  Clock_inst : Clock port map (
    clk => clk
  );
  
  IdRegs32_32_inst : IdRegs32_32 port map (
    -- list connections between master ports and signals
    clk       => clk,
    rs1       => rs1,
    rs2       => rs2,
    wr        => wr,
    cl        => cl,
    rwr       => rwr,
    rwr16     => rwr16,
    rwr_data  => rwr_data,
    rs1_data  => rs1_data,
    rs2_data  => rs2_data
  );
  
  init : process
  -- variable declarations
  begin
    -- code that executes only once    
    wait;                                 -- stop running
  end process init;
  
  always : process
    -- optional sensitivity list
    -- (        )
    -- variable declarations

  begin
    -- code executes for every event on sensitivity list
    report "Testing...";
    wait for 3 * CLOCK_PERIOD / 4;
		
    for clkCount in 0 to 11 loop
      case clkCount mod 12 is
        -- Test #1 upis
        when 0 => 
					rs1 		<= "00000";
					rs2 		<= "00000";
					wr 			<= '1';
					cl 			<= '0';
					rwr 		<= "00000";
					rwr16 	<= '0';
					rwr_data <= (2 downto 0 => '1', others => '0'); -- 7
        -- Test #2 chitanje
				-- Test #3 clear
				when 2 => 
				  rs1 		<= "00000";
					rs2 		<= "00000";
					wr 			<= '0';
					cl 			<= '1';
					rwr 		<= "00000";
					rwr16 	<= '0';
					rwr_data <=(others => '0');					
        -- Test #4 upis 2
        when 3 =>
					rs1 		<= "00000";
					rs2 		<= "00000";
					wr 			<= '1';
					cl 			<= '0';
					rwr 		<= "00100";
					rwr16 	<= '0';
					rwr_data <= (2 => '1', others => '0');					--4
				-- Test #5 upis 3
        when 4 =>
					rs1 		<= "00000";
					rs2 		<= "00000";
					wr 			<= '1';
					cl 			<= '0';
					rwr 		<= "01000";
					rwr16 	<= '0';
					rwr_data <= (3 => '1', others => '0');					--8
        -- Test #6 chitanje
        when 5 =>
					rs1 		<= "00100";
					rs2 		<= "01000";
					wr 			<= '0';
					cl 			<= '0';
					rwr 		<= "00000";
					rwr16 	<= '0';
					rwr_data <= (others => '0');
        -- Test #7 upis u 16b
        when 6 =>
					rs1 		<= "00000";
					rs2 		<= "00000";
					wr 			<= '1';
					cl 			<= '0';
					rwr 		<= "00001";
					rwr16 	<= '1';
					rwr_data <= (others => '1');										--FF
        -- Test #8 chitanje i upis odvojeni
        when 7 =>
					rs1 		<= "00000";
					rs2 		<= "00001";
					wr 			<= '0';
					cl 			<= '0';
					rwr 		<= "00111";
					rwr16 	<= '0';
					rwr_data <= (others => '1');										--FFFF
        -- Test #9 istovremeno chitanje i upis
        when 8 =>
					rs1 		<= "00001";
					rs2 		<= "00100";
					wr 			<= '1';
					cl 			<= '0';
					rwr 		<= "00100";
					rwr16 	<= '0';
					rwr_data <= (20 downto 2 => '1', others => '0');	
        -- Test #10 istovremeno chitanje i upis u 16b
        when 9 =>
					rs1 		<= "00111";
					rs2 		<= "00000";
					wr 			<= '1';
					cl 			<= '0';
					rwr 		<= "00111";
					rwr16 	<= '1';
					rwr_data <= (5 => '1', others => '0');		
        -- Test #11 lazni upis
        when 10 => 
					rs1 		<= "00000";
					rs2 		<= "00000";
					wr 			<= '0';
					cl 			<= '0';
					rwr 		<= "11111";
					rwr16 	<= '1';
					rwr_data <=(0 => '1', others => '0');						-- 1					
        -- Test #N
        when others =>
					rs1 		<= "00000";
					rs2 		<= "00000";
					wr 			<= '0';
					cl 			<= '0';
					rwr 		<= "00000";
					rwr16 	<= '0';
					rwr_data <= (others => '0');
      end case;
			wait for 5 ps;
			report "    rs1 = " & hstr(rs1) & 
             "    rs2 = " & hstr(rs2) &
             "    rwr = " & hstr(rwr) &
             "    Rs1 = " & hstr(rs1_data) &
             "    Rs2 = " & hstr(rs2_data) & 
             "    Rwr = " & hstr(rwr_data);
			wait for CLOCK_PERIOD - 5 ps;
    end loop;
    assert false report "Testing done." severity failure;
    wait;                                 -- stop running
  end process always;
end IdRegs32_32_arch;

configuration IdRegs32_32_vhd_cfg of IdRegs32_32_vhd_tst is 
	for IdRegs32_32_arch
    -- this page is intentionally left blank too
	end for;
end IdRegs32_32_vhd_cfg;